The Small Computer System Interface (SCSI or commonly called the "SCSI bus") is a popular device independent parallel bus. The SCSI bus can, for example, be used to removably connect multiple devices including hard disk drives, printers and other input/output peripheral devices to a host computer. For background, the reader is referred to "Fast Track To SCSI", Integrated Circuits Division of Fujitsu Microelectronics, Inc., published by Prentice Hall (1991), the SCSI-1 specification, and the SCSI-2 specification (documents X3.131 and X3T9.2 of the American National Standards Institute).
FIG. 1 (PRIOR ART) is a simplified block diagram illustrating one possible SCSI bus configuration. Both an initiator device 1 as well as a target device 2 are shown coupled to a SCSI bus 3. SCSI bus 3 comprises nine data conductors (eight for data and one for parity), nine control conductors, and other power and ground conductors. Devices 1 and 2 are coupled in parallel to the bus conductors, corresponding SCSI terminals of each device being coupled to the same corresponding bus conductor. Typically each conductor is resistively coupled to a voltage of an inactive state. To "assert" a signal onto a conductor, a device must drive to conductor to a voltage of an active state against the resistive coupling of the conductor. If not driven, a conductor will return to its inactive state.
Each device connected to a SCSI bus is classified as either an initiator or as a target. Initiator devices cause target devices on the bus to perform commands whereas target devices perform commands for the initiators. There can be multiple initiators and multiple targets on a SCSI bus.
Target device 2 in FIG. 1 is a hard disk computer peripheral device comprising a hard disk controller integrated circuit 4, a buffer memory 5, a first microprocessor 6, a second microprocessor 7, a hard disk 8, head electronics and actuator 9, and read channel electronics 10. If, for example, initiator 1 were to attempt to write data to disk 8, then the initiator 1 would output a write command onto the SCSI bus 3. The SCSI bus is initially in a "bus free phase" in which the SCSI bus is idle. To initiate the write command, initiator 1 asserts a BSY signal onto an OR-tied BSY control conductor of SCSI bus 3, thereby causing the bus to enter an "arbitration bus phase". During the arbitration bus phase, each initiator arbitrates for the bus with the other initiators by asserting the appropriate one of the data conductors of the SCSI bus corresponding with a SCSI identifier (SCSI ID) unique to the initiator. Because each SCSI ID has an assigned priority, the initiator with the highest priority, in this case initiator 1, determines that it has the highest priority by detecting the other data conductors. The highest priority initiator, here initiator 1, asserts a select signal SEL onto a SEL conductor of the bus to indicate to other initiators and targets that the bus is busy.
After winning control of the bus through arbitration, initiator 1 selects the target device of interest, in this case target 2, in a "selection bus phase". Initiator 1 asserts its SCSI ID as well as the SCSI ID of the target onto the data conductors of the SCSI bus. When the target detects its SCSI ID on the data conductors, the target responds by asserting the BSY signal onto the OR-tied BSY conductor. The bus free, arbitration, and selection bus phases are control phases.
With initiator 1 now in control of SCSI bus 3, and with target 2 identified as the target, target 2 requests a SCSI command from initiator 1 in a "command bus phase". The SCSI bus has a C/D signal and an associated C/D conductor for distinguishing control and data on the bus. The C/D signal being asserted indicates control information is being passed over the bus whereas the C/D signal being deasserted indicates data being passed over the bus. The SCSI bus also has an I/O signal and an associated I/O conductor for indicating the direction of flow of information across the bus. The I/O signal being asserted indicates information flow from target to initiator whereas the I/O signal being deasserted indicates information flow from initiator to target. Accordingly, the target asserts the C/D signal indicating control information and deasserts the I/O signal indicating information flow from initiator to target. Initiator 1 then responds by sending the command over the bus to target 2 byte by byte using two control conductors of the SCSI bus, the REQ and ACK conductors, for handshaking. Each SCSI command, called a SCSI command descriptor block (CDB), consists of multiple bytes, either six, ten or twelve bytes. The command contains information which includes a SCSI operation code indicating the type of command to be performed.
FIG. 2A (PRIOR ART) is a diagram illustrating the fields in the SCSI operation code byte of a SCSI command CDB. The first byte, byte 0, of all SCSI commands is a SCSI operation code. A group code of 0 indicates that the command is a six-byte command; a group code of 1 or 2 indicates that the command is a ten-byte command; and a group code of 5 indicates that the command is a twelve-byte command.
FIGS. 2B, 2C and 2D (PRIOR ART) are diagrams illustrating six-byte, ten-byte, and twelve-byte commands, respectively. The transfer length field, if required by the command specified by the command code of the SCSI operation code, specifies the number of blocks (or bytes) transferred upon execution of the command. Whether the transfer length information of the transfer length field is in bytes or blocks is determined by the type of command. If the command is a write command, the command descriptor block includes a logical block address (LBA) of the first block to be transferred as well as the number of blocks to be transferred during execution of the write command.
Hard disk controller integrated circuit 4 comprises a SCSI interface portion 11 for interfacing with the SCSI bus 3, a disk controller portion 12 for interfacing with the hard disk 8, and a buffer manager portion 13 for controlling a flow of data through buffer memory 5 between the SCSI interface portion 11 and disk controller portion 12. It is the SCSI interface portion 11 which receives commands from the SCSI bus 3.
For a write command, the read/write head of disk 8 must usually be moved in a seek operation to an appropriate location on disk where the data is to be written. Accordingly, microprocessor 7 is instructed to move the head to the correct location by microprocessor 6. While the seek operation is being carried out, data can be received from the initiator 1 over SCSI bus 3 for later writing to disk 8. SCSI interface portion 11 therefore configures the buffer manager portion 13 to store incoming data into buffer memory 5.
When the target 2 is ready to receive data, the target 2 deasserts the I/O signal and deasserts the C/D signal thereby causing the bus to enter a "data out phase". Initiator 1 then sends byte after byte of data to target 2 over the SCSI bus using the REQ and ACK signals for handshaking. Successive bytes of data are placed in buffer memory 5. When the seek operation is complete, the disk controller portion 12 begins writing data received from the buffer memory 5 to disk 8.
After, for example, all the data of the write command has been received into buffer memory 5, the target 2 may cause the bus to enter a "status bus phase" by asserting the C/D and I/O signals and by deasserting a signal MSG on an associated control conductor MSG. The target 2 then sends to initiator 1 a status byte indicating whether or not the command was executed without error.
If, for example, the write of information to disk 8 was successful, then target 2 may cause the bus to enter a "message in phase" by asserting the C/D, I/O and MSG signals. With the bus in the message in phase, target 2 may send initiator 1 a SCSI defined message. If, for example, a command complete message is sent, then initiator 1 will be able to examine the status byte after completion of the command. Target 2 releases SCSI bus 3 by releasing the BSY signal whereupon the SCSI bus reenters the bus free phase. Whereas the bus free, arbitration and selection phases are called control phases, the command, data, status and message phases are called information transfer phases.
In order to reduce the cost of a target SCSI hard disk drive peripheral, the first and second microprocessors 6 and 7 may be combined into a single microprocessor. Such a single microprocessor is, however, frequently interrupted to control SCSI bus operations. The response of the microprocessor to other tasks may therefore be undesirably slow. If, for example, a SCSI write command is to be sent to the target, then the microprocessor may be interrupted after the initiator 1 has selected the target. This interrupt allows the microprocessor to set up facilities in the SCSI interface to receive the command bytes. After the command bytes have been received into the SCSI interface (for example into a first-in-first-out memory), the microprocessor is again interrupted. This allows the microprocessor to interpret the meaning of the command bytes.
Because the same type of information may be contained in different ones of the bytes of six-byte, ten-byte and twelve-byte SCSI command descriptor blocks, the microprocessor may read the various bytes of the command descriptor block out of a first-in-first-out memory into which the bytes were initially written, determine what type of information is contained in each byte dependent upon whether the command descriptor block is a six-byte, ten-byte or twelve-byte command descriptor block, and then write selected bytes of the information into predetermined memory locations accessible by the microprocessor for future use.
If the command is determined to be a write command, then the microprocessor would configure the rest of the target including the buffer manager to accommodate the data to be transferred during subsequent execution of the command. Then after the data transfer is complete, the microprocessor is again interrupted by the hard disk controller integrated circuit to indicate that it is time to send the status byte and the command complete message byte to initiator 1. The microprocessor then can load the status byte and command complete message byte into a FIFO and enable an operation to shift to FIFO out, thereby placing the status byte and command complete message bytes onto the SCSI bus. After the placing of status and command complete message bytes onto the SCSI bus, the microprocessor is again interrupted alerting the microprocessor that the operation is completed.
Not only is the microprocessor burdened by the need to determine the locations of different types of information in different types of command descriptor blocks and the need to handle numerous interrupts in the execution of a command, but the microprocessor may also be interrupted in the event that more data is written to the disk drive peripheral than the disk drive peripheral has room to accommodate in its buffer memory. If, for example, the buffer memory 5 is full when additional data is to be received from the bus, then the microprocessor will be interrupted by the hard disk controller integrated circuit. This allows the microprocessor the opportunity to instruct the SCSI interface to disconnect itself from the SCSI bus so that the bus can be used to transfer information between other devices. Then, after the disk drive peripheral again has the ability to receive additional data from the initiator, the microprocessor is again interrupted so that the microprocessor can instruct the SCSI interface portion 11 to again arbitrate for the bus and to reselect the bus in a SCSI "reselection bus phase". Additional interrupts may therefore be involved in disconnecting from the bus and then reconnecting to the bus. Moreover, such disconnecting and reconnecting can occur multiple times when executing a single SCSI command leading to still more microprocessor interrupts. A hard disk controller integrated circuit is therefore desired which reduces microprocessor overhead in parsing command descriptor blocks and which reduces the number of microprocessor interrupts in a SCSI bus target when executing a SCSI command.